Cirrus Logic CS8420 User Manual
Cs8420, Digital audio sample rate converter, Features
Copyright
© Cirrus Logic, Inc. 2007
(All Rights Reserved)
Digital Audio Sample Rate Converter
Features
Complete IEC60958, AES3, S/PDIF, EIAJ
CP1201-compatible Transceiver with
Asynchronous Sample Rate Converter
Flexible 3-wire Serial Digital I/O Ports
8-kHz to 108-kHz Sample Rate Range
1:3 and 3:1 Maximum Input to Output Sample
Rate Ratio
128 dB Dynamic Range
-117 dB THD+N at 1 kHz
Excellent Performance at Almost a 1:1 Ratio
Excellent Clock Jitter Rejection
24-bit I/O Words
Pin and Microcontroller Read/Write Access to
Channel Status and User Data
Microcontroller and Stand-Alone Modes
General Description
The CS8420 is a stereo digital audio sample rate con-
verter (SRC) with AES3-type and serial digital audio
inputs, AES3-type and serial digital audio outputs, and
includes comprehensive control ability via a 4-wire mi-
crocontroller port. Channel status and user data can be
assembled in block-sized buffers, making
read/modify/write cycles easy.
Digital audio inputs and outputs may be 24, 20, or 16
bits. The input data can be completely asynchronous to
the output data, with the output data being synchronous
to an external system clock.
The CS8420 is available in a 28-pin SOIC package in
both Commercial (-10º to +70º C) and Automotive
grades (-40º to +85º C). The CDB8420 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions.
Please refer to
“Ordering Information” on page 93
for or-
dering information.
Target applications include CD-R, DAT, MD, DVD and
VTR equipment, mixing consoles, digital audio trans-
mission equipment, high-quality D/A and A/D
converters, effects processors, and computer audio
systems.
Serial
Audio
Input
Clock &
Data
Recovery
Misc.
Control
AES3
S/PDIF
Encoder
Serial
Audio
Output
Receiver
AES3
S/PDIF
Decoder
Sample
Rate
Converter
C & U bit
Data
Buffer
Control
Port &
Registers
Output
Clock
Generator
RXN
RXP
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
TXP
TXN
RST
OMCK
EMPH U TCBL SDA/
CDOUT
SCL/
CCLK
AD1/
CDIN
AD0/
CS
INT
VA+ AGND FILT
RERR
VD+ DGND
H/S
RMCK
Driver
APRIL '07
DS245F4
CS8420
Document Outline
- 1. Characteristics and Specifications
- Specified Operating Conditions
- Absolute Maximum Ratings
- Performance Specifications
- Digital Filter Characteristics
- DC Electrical Specifications
- Digital Input Characteristics
- Digital Interface Specifications
- Transmitter Characteristics
- Switching Characteristics
- Switching Characteristics - Serial Audio Ports
- Switching Characteristics - Control Port - SPI™ Mode
- Switching Characteristics - Control Port - I·C® Mode
- 2. Typical Connection Diagram
- 3. General Description
- 4. Data I/O Flow and Clocking Options
- Figure 6. Software Mode Audio Data Flow Switching Options
- Figure 7. CS8420 Clock Routing
- Figure 8. Serial Audio Input, using PLL, SRCEnabled
- Figure 9. Serial Audio Input, No PLL, SRC Enabled
- Figure 10. AES3 Input, SRC Enabled
- Figure 11. Serial Audio Input, AES3 Input Clock Source, SRC Enabled
- Figure 12. Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock
- Figure 13. AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out
- Figure 14. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC
- Figure 15. AES3 Input to Serial Audio Output Only
- Figure 16. Input Serial Port to AES3 Transmitter
- 5. Sample Rate Converter (SRC)
- 6. Three-wire Serial Audio Ports
- 7. AES3 Transmitter and Receiver
- 8. AES3 Transmitter and Receiver
- 9. Control Port Description and Timing
- 10. Control Port Register Bit Definitions
- 10.1 Memory Address Pointer (MAP)
- 10.2 Miscellaneous Control 1 (01h)
- 10.3 Miscellaneous Control 2 (02h)
- 10.4 Data Flow Control (03h)
- 10.5 Clock Source Control (04h)
- 10.6 Serial Audio Input Port Data Format (05h)
- 10.7 Serial Audio Output Port Data Format (06h)
- 10.8 Interrupt 1 Register Status (07h) (Read Only)
- 10.9 Interrupt Register 2 Status (08h) (Read Only)
- 10.10 Interrupt 1 Register Mask (09h)
- 10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh)
- 10.12 Interrupt 2 Register Mask (0Ch)
- 10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)
- 10.14 Receiver Channel Status (0Fh) (Read Only)
- 10.15 Receiver Error (10h) (Read Only)
- 10.16 Receiver Error Mask (11h)
- 10.17 Channel Status Data Buffer Control (12h)
- 10.18 User Data Buffer Control (13h)
- 10.19 Sample Rate Ratio (1Eh) (Read Only)
- 10.20 C-Bit or U-Bit Data Buffer (20h - 37h)
- 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only)
- 11. System and Applications Issues
- 11.1 Reset, Power Down and Start-up Options
- 11.2 Transmitter Startup
- 11.3 SRC Invalid State
- 11.4 C/U Buffer Data Corruption
- 11.5 Block-Mode U-Data D-to-E Buffer Transfers
- 11.6 ID Code and Revision Code
- 11.7 Power Supply, Grounding, and PCB layout
- 11.8 Synchronization of Multiple CS8420s
- 11.9 Extended Range Sample Rate Conversion
- 12. Software Mode - Pin Description
- 13. Hardware Modes
- 14. External AES3/SPDIF/IEC60958 Transmitter and Receiver Components
- 15. Channel Status and User Data Buffer Management
- 15.1 AES3 Channel Status(C) Bit Management
- 15.2 AES3 User (U) Bit Management
- 16. PLL Filter
- 17. Parameter Definitions
- 18. Package Dimensions
- 19. Ordering Information
- 20. Revision History