Cirrus Logic CS8420 - Manual (Page 74)

74 DS245F4
CS8420
13.7 Hardware Mode 6 Description
(AES3 Transmitter Only)
Hardware Mode 6 data flow is shown in Figure 29 . Audio data is input via the serial audio input port and
routed to the AES3 transmitter.
The transmitted channel status, user, and validity data may be input in two alternative methods, determined
by the state of the CEN pin. Mode 6A is selected when the CEN pin is low. In mode 6A, the user data and
validity bit are input via the U and V pins, clocked by both edges of ILRCK. The channel status data is de-
rived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins.
Table 15 shows how the COPY/C and
ORIG pins map to channel status bits. In consumer mode, the transmitted category code shall be set to
Sample Rate Converter (0101100b).
Mode 6B is selected when the CEN pin is high. In mode 6B, the channel status, user data and validity bit
are input serially via the COPY/C, U, and V pins. These pins are clocked by both edges of ILRCK (if the port
is in Master mode).
Figure 20 shows the timing requirements.
The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD
pin. The serial audio input port data format is selected as shown in
Table 15 , and may be set to master or
slave by the state of the APMS input pin.
The following pages contain detailed pin descriptions for Hardware mode 6.
AES3
Encoder
& Tx Serial
Audio
Input
C, U, V Data Buffer
ILRCK
ISCLK
TXP
COPY/C ORIG EMPH AUDIO TCBL
DFC0 DFC1 S/AES
VD+
H/S
Output
Clock
Source
OMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
VD+
SDIN
SFMT1 SFMT0
VD+
FILT
TXN
CEN
U
V
VD+
TCBLD APMS
Figure 29. Hardware Mode 6 - AES3 Transmitter Only