Cirrus Logic CS8420 - Manual (Page 33)

DS245F4 33
CS8420
Addr
(HEX)
Function 7 6 5 4 3 2 1 0
01 Control 1 SWCLK VSET MUTESAO MUTEAES DITH INT1 INT0 TCBLD
02 Control 2 TRUNC HOLD1 HOLD0 RMCKF MMR MMT MMTCS MMTLR
03 Data Flow Control AMLL TXOFF AESBP TXD1 TXD0 SPD1 SPD0 SRCD
04 Clock Source Control 0 RUN CLK1 CLK0 OUTC INC RXD1 RXD0
05 Serial Input Format SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL
06 Serial Output Format SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL
07 Interrupt 1 Status TSLIP OSLIP SRE OVRGL OVRGR DETC EFTC RERR
08 Interrupt 2 Status 0 0 VFIFO REUNLOCK DETU EFTU QCH UOVW
09 Interrupt 1 Mask TSLIPM OSLIPM SREM OVRGLM OVRGRM DETCM EFTCM RERRM
0A Interrupt 1 Mode (MSB) TSLIP1 OSLIP1 SRE1 OVRGL1 OVRGR1 DETC1 EFTC1 RERR1
0B Interrupt 1 Mode (LSB) TSLIP0 OSLIP0 SRE0 OVRGL0 OVRGR0 DETC0 EFTC0 RERR0
0C Interrupt 2 Mask 0 0 VFIFOM REUNLOCKM DETUM EFTUM QCHM UOVWM
0D Interrupt 2 Mode (MSB) 0 0 VFIFO1 REUNLOCK1 DETU1 EFTU1 QCH1 UOVW1
0E Interrupt 2 Mode (LSB) 0 0 VFIFO0 REUNLOCK0 DETU0 EFTU0 QCH0 UOVW0
0F Receiver CS Data AUX3 AUX2 AUX1 AUX0 PRO AUDIO COPY ORIG
10 Receiver Errors 0 QCRC CCRC UNLOCK V CONF BIP PAR
11 Receiver Error Mask 0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM
12 CS Data Buffer Control 0 0 BSEL CBMR DETCI EFTCI CAM CHS
13 U Data Buffer Control 0 0 0 UD UBM1 UBM0 DETUI EFTUI
14-1D Q Sub-Code Data
1E Sample Rate Ratio SRR7 SRR6 SRR5 SRR4 SRR3 SRR2 SRR1 SRR0
20-37 C or U Data Buffer
7F ID and Version ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0
Table 4. Summary of all Bits in the Control Register Map