Cirrus Logic CS8420 - Manual (Page 44)

44 DS245F4
CS8420
10.15 Receiver Error (10h) (Read Only)
This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on
occurrence of the error, and will stay high until the register is read. Reading the register resets
all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error
mask register will always be 0 in this register. This register defaults to 00.
QCRC Q-subcode data CRC error has occurred. Updated on Q-subcode block boundaries.
0 - No error
1 - Error
CCRC Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries.
This bit is valid in Professional mode only.
0 - No error
1 - Error
UNLOCK PLL lock status bit. Updated on CS block boundaries.
0 - PLL locked
1 - PLL out of lock
V Received AES3 Validity bit status. Updated on sub-frame boundaries.
0 - Data is valid and is normally linear coded PCM audio
1 - Data is invalid, or may be valid compressed audio
CONF Confidence bit. Updated on sub-frame boundaries.
0 - No error
1 - Confidence error. This indicates that the received data eye opening is less than
half a bit period, indicating a poor link that is not meeting specifications.
BIP Bi-phase error bit. Updated on sub-frame boundaries.
0 - No error
1 - Bi-phase error. This indicates an error in the received bi-phase coding.
PAR Parity bit. Updated on sub-frame boundaries.
0 - No error
1 - Parity error
7 6 5 4 3 2 1 0
0 QCRC CCRC UNLOCK V CONF BIP PAR