Cirrus Logic CS8420 - Manual (Page 45)

DS245F4 45
CS8420
10.16 Receiver Error Mask (11h)
The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis-
ter. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will
appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and
will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set
to 0, the error is considered masked, meaning that its occurrence will not appear in the receiver
error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect
the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they
do not affect the current audio sample even when unmasked. This register defaults to 00.
10.17 Channel Status Data Buffer Control (12h)
BSEL Selects the data buffer register addresses to contain User data or Channel Status data
0 - Data buffer address space contains Channel Status data (default)
1 - Data buffer address space contains User data
CBMR Control for the first 5 bytes of channel status “E” buffer
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
(default)
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
DETCI D to E C-data buffer transfer inhibit bit.
0 - Allow C-data D to E buffer transfers (default)
1 - Inhibit C-data D to E buffer transfers
EFTCI E to F C-data buffer transfer inhibit bit.
0 - Allow C-data E to F buffer transfers (default)
1 - Inhibit C-data E to F buffer transfers
CAM C-data buffer control port access mode bit
0 - One byte mode
1 - Two byte mode
CHS Channel select bit
0 - Channel A information is displayed at the EMPH pin and in the receiver channel
status register. Channel A information is output during control port reads when
CAM is set to 0 (One Byte Mode)
1 - Channel B information is displayed at the EMPH pin and in the receiver channel
status register. Channel B information is output during control port reads when
CAM is set to 0 (One Byte Mode)
7 6 5 4 3 2 1 0
0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM
7 6 5 4 3 2 1 0
0 0 BSEL CBMR DETCI EFTCI CAM CHS