Pll filter, 1 general, Figure 41. pll block diagram – Cirrus Logic CS8420 User Manual
Page 87: 2 external filter components, 1 general 16.2 external filter components, Figure 41.pll block diagram, Please see
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CS8420
16. PLL FILTER
16.1
General
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure
41 is a simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream,
it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, F
S
. When
the PLL is locked to ILRCK, it is updated at F
S
so that the duty cycle of the input doesn’t affect jitter.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is impor-
tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown
in
and
. In addition, the PLL has been designed to use only the preambles of the AES3
stream to provide lock update information to the PLL. This results in the PLL being immune to data-depen-
dent jitter effects because the AES3 preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.
If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will
only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample
rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8420
clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its
wide lock range mode and re-acquire a new nominal center sample rate.
16.2
External Filter Components
16.2.1
General
The PLL behavior is affected by the external filter component values.
shows the rec-
ommended configuration of the two capacitors and one resistor that comprise the PLL filter. In
and
, the component values shown for the 32 to 96 kHz range have the highest corner frequency
jitter attenuation curve, takes the shortest time to lock, and offers the best output jitter performance. The
component values shown in
and
for the 8 to 96 kHz range allows the lowest input sam-
ple rate to be 8 kHz, and increases the lock time of the PLL. Lock times are worst case for an Fsi transition
of 96 kHz.
Phase
Comparator
and Charge Pump
÷N
VCO
RMCK
INPUT
Crip
Cfilt
Rfilt
Figure 41. PLL Block Diagram