Cirrus Logic CS8420 - Manual (Page 90)

90 DS245F4
CS8420
16.3.4 Jitter Tolerance
Shown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4
specification. CS8420 parts used with the appropriate external PLL component values (as noted in
Table 19 ) have been tested to pass this template.
16.3.5 Jitter Attenuation
Shown in Figure 44 and Figure 45 are jitter attenuation plots for the various revisions of the CS8420 when
used with the appropriate external PLL component values (as noted in Table 19 ). The AES3 and
IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz or for lock-
ing to the ILRCK input. These specifications state a maximum of 2 dB jitter gain or peaking.
Figure 43. Jitter Tolerance Template
10 −1 10 0 10 1 10 2 10 3 10 4 10 5
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Jitter Attenuation (dB)
10 −1 10 0 10 1 10 2 10 3 10 4 10 5
−25
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Jitter Attenuation (dB)
Figure 44. Revision D Jitter Attenuation Figure 45. Revision D1 Jitter Attenuation