Figure 20, Cs8420 – Cirrus Logic CS8420 User Manual
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DS245F4
CS8420
Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data
VCU[0]
VCU[1]
VCU[2]
VCU[3]
VCU[4]
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
Data [0]
Data [1]
Data [2]
Data [3]
Data [4]
Z
Y
X
Y
X
AES3 Transmitter in Stereo Mode
U[0]
U[2]
VLRCK
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
Data [0]*
Data [2]*
Data [4]*
Z
Y
X
*Assume MMTLR = 0
Tsetup = > 7.5 % AES3 frame time
Thold = 0
Tsetup
Thold
Data [1]*
Data [3]*
Data [5]*
Z
Y
X
AES3 Transmitter in Mono Mode
*Assume MMTLR = 1
Tsetup = > 15 % AES3 frame time
Thold = 0
Tth
Tth > 3 OMCK if TCBL is Input
Tth > 3 OMCK if TCBL is Input
Tth
U
Input
TCBL
In or Out
SDIN
Input
TXP(N)
Output
TXP(N)
Output
VLRCK
VCU
Input
SDIN
Input
TCBL
In or Out
TXP(N)
.
VLRCK duty cycle is 50%
In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.
If the serial audio input port is in master mode and TCBL is an input, the VLRCK=ILRCK if SILRPOL=0 and
VLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing.
If the serial audio input port is in slave mode and TCBL is an output, the VLRCK=ILRCK if SILRPOL=0 and
VLRCK = ILRCK if SILRPOL = 1.
VLRCK = ILRCK if SILRPOL = 1.