Document Outline

• 1. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • Performance Specifications
  • Digital Filter Characteristics
  • DC Electrical Specifications
  • Digital Input Characteristics
  • Digital Interface Specifications
  • Transmitter Characteristics
  • Switching Characteristics
  • Switching Characteristics - Serial Audio Ports
    • Figure 1. Audio Port Master Mode Timing
    • Figure 2. Audio Port Slave Mode and Data Input Timing
  • Switching Characteristics - Control Port - SPI™ Mode
    • Figure 3. SPI Mode Timing
  • Switching Characteristics - Control Port - I·C® Mode
    • Figure 4. I·C Mode Timing
• 2. Typical Connection Diagram
  • Figure 5. Recommended Connection Diagram for Software Mode
• 3. General Description
• 4. Data I/O Flow and Clocking Options
  • Figure 6. Software Mode Audio Data Flow Switching Options
  • Figure 7. CS8420 Clock Routing
  • Figure 8. Serial Audio Input, using PLL, SRCEnabled
  • Figure 9. Serial Audio Input, No PLL, SRC Enabled
  • Figure 10. AES3 Input, SRC Enabled
  • Figure 11. Serial Audio Input, AES3 Input Clock Source, SRC Enabled
  • Figure 12. Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock
  • Figure 13. AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out
  • Figure 14. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC
  • Figure 15. AES3 Input to Serial Audio Output Only
  • Figure 16. Input Serial Port to AES3 Transmitter
• 5. Sample Rate Converter (SRC)
  • 5.1 Dither
  • 5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register
• 6. Three-wire Serial Audio Ports
  • Figure 17. Serial Audio Input Example Formats
  • Figure 18. Serial Audio Output Example Formats
• 7. AES3 Transmitter and Receiver
  • 7.1 AES3 Receiver
    • 7.1.1 PLL, Jitter Attenuation, and Varispeed
    • 7.1.2 OMCK Out On RMCK
    • 7.1.3 Error Reporting and Hold Function
    • 7.1.4 Channel Status Data Handling
    • 7.1.5 User Data Handling
      • Figure 19. AES3 Receiver Timing for C & U Pin Output Data
    • 7.1.6 Non-Audio Auto Detection
  • 7.2 AES3 Transmitter
    • 7.2.1 Transmitted Frame and Channel Status Boundary Timing
    • 7.2.2 TXN and TXP Drivers
  • 7.3 Mono Mode Operation
    • Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data
    • Figure 21. Mono Mode Operation Compared to Normal Stereo Operation
• 8. AES3 Transmitter and Receiver
  • 8.1 Sample Rate Converter
    • Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN
    • Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK
  • 8.2 Non-SRC Delay
    • Table 3. Non-SRC Delay
• 9. Control Port Description and Timing
  • 9.1 SPI Mode
    • Figure 22. Control Port Timing in SPI Mode
  • 9.2 I·C Mode
    • Figure 23. Control Port Timing in I·C Mode
  • 9.3 Interrupts
• 10. Control Port Register Bit Definitions
  • 10.1 Memory Address Pointer (MAP)
    • Table 4. Summary of all Bits in the Control Register Map
  • 10.2 Miscellaneous Control 1 (01h)
  • 10.3 Miscellaneous Control 2 (02h)
  • 10.4 Data Flow Control (03h)
  • 10.5 Clock Source Control (04h)
  • 10.6 Serial Audio Input Port Data Format (05h)
  • 10.7 Serial Audio Output Port Data Format (06h)
  • 10.8 Interrupt 1 Register Status (07h) (Read Only)
  • 10.9 Interrupt Register 2 Status (08h) (Read Only)
  • 10.10 Interrupt 1 Register Mask (09h)
  • 10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh)
  • 10.12 Interrupt 2 Register Mask (0Ch)
  • 10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)
  • 10.14 Receiver Channel Status (0Fh) (Read Only)
  • 10.15 Receiver Error (10h) (Read Only)
  • 10.16 Receiver Error Mask (11h)
  • 10.17 Channel Status Data Buffer Control (12h)
  • 10.18 User Data Buffer Control (13h)
  • 10.19 Sample Rate Ratio (1Eh) (Read Only)
  • 10.20 C-Bit or U-Bit Data Buffer (20h - 37h)
  • 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only)
• 11. System and Applications Issues
  • 11.1 Reset, Power Down and Start-up Options
  • 11.2 Transmitter Startup
  • 11.3 SRC Invalid State
  • 11.4 C/U Buffer Data Corruption
  • 11.5 Block-Mode U-Data D-to-E Buffer Transfers
  • 11.6 ID Code and Revision Code
  • 11.7 Power Supply, Grounding, and PCB layout
  • 11.8 Synchronization of Multiple CS8420s
  • 11.9 Extended Range Sample Rate Conversion
• 12. Software Mode - Pin Description
• 13. Hardware Modes
  • 13.1 Overall Description
    • 13.1.1 Hardware Mode Definitions
      • Table 5. Hardware Mode Definitions
    • 13.1.2 Serial Audio Port Formats
      • Table 6. Serial Audio Output Formats Available in Hardware Mode
      • Table 7. Serial Audio Input Formats Available in Hardware Mode
  • 13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)
    • Figure 24. Hardware Mode 1 - Default Data Flow, AES3 Input
    • Table 8. Hardware Mode 1 Start-Up Options
    • 13.2.1 Pin Description - Hardware Mode 1
  • 13.3 Hardware Mode 2 Description
    • Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input
    • Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function
    • Table 10. HW Mode 2 Serial Audio Port Format Selection
    • Table 11. Hardware Mode 2 Start-Up Options
    • 13.3.1 Pin Description - Hardware Mode 2
  • 13.4 Hardware Mode 3 Description
    • Figure 26. Hardware Mode 3 - Transceive Data Flow, with SRC
    • Table 12. Hardware Mode 3 Start-Up Options
    • 13.4.1 Pin Description - Hardware Mode 3
  • 13.5 Hardware Mode 4 Description
    • Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC
    • Table 13. Hardware Mode 4 Start-Up Options
    • 13.5.1 Pin Description - Hardware Mode 4
  • 13.6 Hardware Mode 5 Description
    • Figure 28. Hardware Mode 5 - AES3 Receiver Only
    • Table 14. Hardware Mode 5 Start-Up Options
    • 13.6.1 Pin Description - Hardware Mode 5
  • 13.7 Hardware Mode 6 Description
    • Figure 29. Hardware Mode 6 - AES3 Transmitter Only
    • Table 15. HW 6 COPY/C and ORIG Pin Function
    • Table 16. HW 6 Serial Port Format Selection
    • 13.7.1 Pin Description - Hardware Mode 6
• 14. External AES3/SPDIF/IEC60958 Transmitter and Receiver Components
  • 14.1 AES3 Transmitter External Components
    • Figure 30. Professional Output Circuit
    • Figure 31. Consumer Output Circuit
    • Figure 32. TTL/CMOS Output Circuit
  • 14.2 AES3 Receiver External Components
    • Figure 33. Professional Input Circuit
    • Figure 34. Transformerless Professional Input Circuit
    • Figure 35. Consumer Input Circuit
    • Figure 36. TTL/CMOS Input Circuit
  • 14.3 Isolating Transformer Requirements
• 15. Channel Status and User Data Buffer Management
  • 15.1 AES3 Channel Status(C) Bit Management
    • Figure 37. Channel Status Data Buffer Structure
    • 15.1.1 Manually Accessing the E Buffer
      • Figure 38. Channel Status Block Handling When Fso is Not Equal to Fsi
      • Figure 39. Flowchart for Reading the E Buffer
      • Figure 40. Flowchart for Writing the E Buffer
    • 15.1.2 Reserving the First 5 Bytes in the E Buffer
    • 15.1.3 Serial Copy Management System(SCMS)
    • 15.1.4 Channel Status Data E Buffer Access
    • 15.1.5 One-Byte Mode
    • 15.1.6 Two-Byte Mode
  • 15.2 AES3 User (U) Bit Management
    • 15.2.1 Mode 1: Transmit All Zeros
    • 15.2.2 Mode 2: Block Mode
    • 15.2.3 IEC60958 Recommended U Data Format for Consumer Applications
    • 15.2.4 Mode (3): Reserved
    • 15.2.5 Mode (4): IEC Consumer B
• 16. PLL Filter
  • 16.1 General
    • Figure 41. PLL Block Diagram
  • 16.2 External Filter Components
    • 16.2.1 General
    • 16.2.2 Capacitor Selection
    • 16.2.3 Circuit Board Layout
      • Figure 42. Recommended Layout Example
  • 16.3 Component Value Selection
    • 16.3.1 Identifying the Part Revision
      • Table 17. Second Line Part Marking
    • 16.3.2 Locking to the RXP/RXN Receiver Inputs
      • Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz
      • Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz*
    • 16.3.3 Locking to the ILRCK Input
      • Table 20. Locking to the ILRCK Input
    • 16.3.4 Jitter Tolerance
      • Figure 43. Jitter Tolerance Template
    • 16.3.5 Jitter Attenuation
      • Figure 44. Revision D Jitter Attenuation
      • Figure 45. Revision D1 Jitter Attenuation
• 17. Parameter Definitions
• 18. Package Dimensions
  • Thermal Characteristics and Specifications
• 19. Ordering Information
• 20. Revision History