ADLINK PCM-9112+ - Manual (Page 40)

32 • Registers
3.8 Internal Timer/Counter Register
Two 8254 counters are used to periodically trigger the A/D conversion, A
third counter is left free for user applications. The 8254 occupies four I/O
address locations in the PCI-9112 as shown below. Users can refer to NEC's
or Intel's data sheet for a full description of the 8254 features.
Address: BASE + 0 ~ BASE + F
Attribute: read / write
Data Format:
Base + 0 Counter 0 Register (R/W)
Base + 4 Counter 1 Register (R/W)
Base + 8 Counter 2 Register (R/W)
Base + C 8254 CONTROL BYTE (W)
3.9 High Level Programming
To operate the PCI-9112, you should by-pass the detailed register structures
and control your PCI-9112 card directly via the high-level Application-
Programming-Interface (API). The software Libraries, including DOS Library
for Borland C++ and DLL driver for Windows-95/98, are included in the CD.
For more detailed information, please refer to Chapter 5 “C/C++ Software
Library”.
3.10 Low Level Programming
To operate the PCI-9112, users do not need to understand how to write a
hardware dependent low-level program. As it is very complex to program the
PCI controller, information regarding the PCI controller is beyond the scope
of this manual. We do not recommend users to program applications based
on low-level programming. The PCI controller used in the PCI-9112 is an
AMCC-S5933. For more information on the S5933 PCI controller please visit
the web site: www.amcc.com