ADLINK PCM-9112+ - Manual (Page 50)

42 • Operation Theory
• Programmable baud rate generator
• Event counter
• Binary rate multiplier
• Real-time clock
• Digital one-shot
• Motor control
Pacer Trigger Source
Counter 1 and 2 are cascaded together to generate the timer pacer trigger for
A/D conversion. The frequency of the pacer trigger is software controllable.
The maximum pacer signal rate is 2MHz/4=500KHz which exceeds the
maximum A/D conversion rate of the PCI-9112. The minimum signal rate is
2MHz/65536/65536, which is a very slow, and users may never use it.
General Purpose Timer/ Counter
Counter 0 is free for users' applications. The clock source, gate control
signal and the output signal are sent to the connector CN3. The general-
purpose timer / counter can be used as an event counter, or used for
measuring frequency, or others functions.
I/O Address
The 8254 in the PCI-9112 occupy 4 I/O addresses as shown below.
BASE + 0 LSB OR MSB OF COUNTER 0
BASE + 1 LSB OR MSB OF COUNTER 1
BASE + 2 LSB OR MSB OF COUNTER 2
BASE + 3 CONTROL BYTE
The programming of the 8254 is control by the registers BASE+0 to BASE+3.
The functionality of each register has been specified in this section. For more
information, please refer to the 8254 handbook or visit the following web sit at.
http://www.tundra.com