ADLINK PCM-9112+ - Manual (Page 45)

Operation Theory • 37
Software trigger
This trigger source is software controllable. That is, the A/D conversion starts
when any value is written into the software trigger register (BASE+20). This
trigger mode is suitable for low speed A/D conversions. Under this mode, the
timing of the A/D conversion is fully controlled by the software. However, it is
difficult to control a fixed A/D conversion rate unless another timer interrupt
service routine is used to generate a fixed rate trigger.
Timer Pacer Trigger
An on-board 8254 timer / counter chip is used to provide a trigger source for
A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded
together to generate trigger pulses with precise periods. Please refer to
section 4.5 for the 8254 architecture. This mode is ideal for high speed A/D
conversion. It can be combined with the DMA bus mastering or the interrupt
data transfer. It's recommended that this mode be used if your application
needs a fixed and precise A/D sampling rate.
External Trigger
Through pin-17 of CN3 (ExtTrig), the A/D conversion can also be performed
when a rising edge of an external signal is present. The conversion rate of
this mode is more flexible than the previous two modes, because the user
can control the external signal with the external device. The external trigger
can be combined with the DMA transfer, interrupt data transfer, or even
program polling data transfer. Generally, the interrupt data transfer is often
used when external trigger mode is used.
4.2.3 A/D Data Transfer Modes
On the PCI-9112, any of the three A/D data transfer modes can be used
when a conversion is completed. The Data Transfer Mode is controlled by
the A/D mode control bits (INTX, DMAX) of the A/D control register
(BASE+18). The different transfer modes are specified below:
Software Data Transfer (DRDY)
Usually, this mode is used with software A/D trigger mode. The conversion
starts when it receives a software trigger, the software then polls the DRDY
bit on the A/D Status register until it becomes high. When it is low, the A/D
data is read, and the DRDY bit will be cleared to indicate the data transfer is
completed.
It is possible to read A/D converted data without polling. The A/D conversion
time takes no more then 8µs on PCI-9112 card. Hence, after a software
trigger, the software can wait for at least 8µs then read the A/D register
without polling.