ADLINK PCI-7442 - Manual (Page 48)

36 Register Format
Interrupt Status, COS INT Control Read Back Registers
When any COS interrupts occur, these registers provide informa-
tion for you to recognize the interrupt status and the interrupt setup
condition read back.
Address: BASE+0x06h
Reset Value: 0x0000h
Read/Write: R
-- -- -- -- -- -- CIS1 CIS0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
COS0E -- -- -- -- -- -- --
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit14 - 12 Not used
Bit0 CIS0: COS 0 interrupt status
1: COS interrupt assert
0: COS interrupt no assert
Bit1 CIS1: COS 1 interrupt status
1: COS interrupt assert
0: COS interrupt no assert
Bit15 COS0E: COS 0 interrupt enable status
1: COS 0 interrupt enabled
0: COS 0 interrupt disabled
Address: BASE+0x46h
Reset Value: 0x0000h
Read/Write: R
-- -- -- -- -- -- -- --
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
COS1E -- -- -- -- -- -- --
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit14 - 0 Not used
Bit15 COS1E: COS 1 interrupt enable status
1: COS 1 interrupt enabled
0: COS 1 interrupt disabled