ADLINK PCI-7442 - Manual (Page 66)

54 Register Format
When COS occurs, the COS Latch registers also latch the
DI[31..0], DI[63..32],DI[95..64], and DI[127..96] data, respectively.
Once you clear the interrupt request, the COS Latch register
clears automatically. Since you can read these registers to know
the statuses after interrupts, these registers free the CPU from
constantly polling all inputs and enable the system to handle more
tasks.
Address R/W Value Mapping (MSB----LSB)
BASE+0x08h R IDI_COS_LATCH_DATA[15...0]
BASE+0x0Ah R IDI_COS_LATCH_DATA[31...16]
BASE+0x48h R IDI_COS_LATCH_DATA[47...32]
BASE+0x4Ah R IDI_COS_LATCH_DATA[63...48]
BASE+0x88h R IDI_COS_LATCH_DATA[79...64]
BASE+0x8Ah R IDI_COS_LATCH_DATA[95...80]
BASE+0xC8h R IDI_COS_LATCH_DATA[111...96]
BASE+0xCAh R IDI_COS_LATCH_DATA[127...112]
Bit value: 1: The input is ON.
0: The input is OFF. (Initial value)