ADLINK PCI-7442 - Manual (Page 50)

38 Register Format
TTL IO Setup, Status, DO and DI Registers
The PCI-7442 provides an extra 32-channel TTL I/O function for
optional applications. These TTL I/O channels are divided among
two 16-bits banks and are divided between two connectors: JP3
and JP4. You may choose the direction of each TTL channel any
time by setting up the two-bank TTL IO setup register.
When you set up the direction of TTL I/O channels, the statuses of
setting can be read back through TTL IO Status Read Back Regis-
ter in each back. You can read back the I/O direction statuses to
check if the settings are correct.
When the I/O direction setting is output, you can send out data
through the TTL I/O output channel.
Address R/W Value Mapping (MSB----LSB)
BASE+0x0Ch W TTL_IO_SETUP[15…0]
BASE+0x4Ch W TTL_IO_SETUP[31..16]
Bit value: 0: I/O direction is input (default).
1: I/O direction is output.
Address R/W Value Mapping (MSB----LSB)
BASE+0x0Ch R TTL_IO_STATUS[15…0]
BASE+0x4Ch R TTL_IO_STATUS[31...16]
Bit value: 0: I/O direction is input (default).
1: I/O direction is output.
Address R/W Value Mapping (MSB----LSB)
BASE+0x0Eh W TTL_IO_DO[15…0]
BASE+0x4Eh W TTL_IO_DO[31...16]
Bit value: 0: Output is low (default).
1: Output is high.