ADLINK PCI-7442 - Manual (Page 77)

Register Format 65
TTL IO Setup, Status, DO and DI Registers
The PCI-7444 provides an extra 32-CH TTL I/O function for
optional applications. These TTL I/O channels are divided into two
16-bit banks. These channels are divided between two connec-
tors: JP3 and JP4. You can choose the direction of each TTL
channel any time by setting up the two-bank TTL IO setup register.
When you set up the direction of TTL I/O channels, the statuses of
setting can be read back through TTL IO Status Read Back Regis-
ters. You can read back the I/O direction statuses to check if the
directions meet your need.
When the I/O direction setting is output, you can send out data
through the TTL I/O output channel.
Address R/W Value Mapping (MSB----LSB)
BASE+0x3C W TTL_IO_SETUP[15…0]
BASE+0x3E W TTL_IO_SETUP[31...16]
Bit value: 0: I/O direction is input. (Default)
1: I/O direction is output.
Address R/W Value Mapping (MSB----LSB)
BASE+0x3C R TTL_IO_STATUS[15…0]
BASE+0x3E R TTL_IO_STATUS[31...16]
Bit value: 0: I/O direction is input. (Default)
1: I/O direction is output.
Address R/W Value Mapping (MSB----LSB)
BASE+0x40 W TTL_IO_DO[15…0]
BASE+0x42 W TTL_IO_DO[31...16]
Bit value: 0: Output in low logic. (Default)
1: Output in high logic.