ADLINK PCI-7442 - Manual (Page 60)

48 Register Format
COS Interrupt Control Registers
The interrupt mode in the PCI-7443 is disabled by default. You can
write the registers listed below to enable the interrupt function. In
interrupt mode, you may enable the COS (Change of State) inter-
rupt function to monitor the statuses of enabled input channels
whenever the statuses change from 0 to 1 or from 1 to 0.
After processing the interrupt request event, you must clear the
interrupt request in order to handle another interrupt request. Take
note that it takes time for a system to clear the interrupt. Also, any
uncleared COS interrupt that comes before the previous interrupt
is neglected. To clear the interrupt request, write 1 to the corre-
sponding bit.
The COS interrupt is enabled by four registers. Because the 128
digital inputs are divided into four 32-bit onboard buses, every 32
inputs are connected to a CPLD. When users enable COS inter-
rupt EA0 (BASE+0x06h), the first CPLD (CPLD0) produces inter-
rupt signal while the first 32-bit inputs IDI[31..0] have change of
state. When users enable COS interrupt EA1 (BASE+0x46h), the
second CPLD (CPLD1) produces interrupt signal while the second
32-bit inputs IDI[63..32] have change of state. When users enable
COS interrupt EA2 (BASE+0x86h), the third CPLD (CPLD2) pro-
duces interrupt signal while the second 32-bit inputs IDI[95..64]
have change of state. When users enable COS interrupt EA3
(BASE+0xC6), the fourth CPLD (CPLD3) produces interrupt signal
while the second 32-bit inputs IDI[127..96] have change of state.
Address: BASE+0x06h
Reset Value: 0x0000h
Read/Write: W
-- -- -- -- -- -- -- CLR0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-- -- -- -- -- -- -- EA0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit15 - 9 Not used
Bit7 - 1 Not used
Bit0 CLR0: COS 0 interrupt clear
1: Clear; 0: No effect