ADLINK PCI-7442 - Manual (Page 63)

Register Format 51
Interrupt Status, COS INT Control Read Back Registers
When any COS interrupt occurs, these registers provide informa-
tion to recognize the interrupt status and the interrupt setup condi-
tion read back.
Address: BASE+0x06h
Reset Value: 0x0000h
Read/Write: R
-- -- -- -- C3IS C2IS C1IS C0IS
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
COS0E -- -- -- -- -- -- --
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit14 - 4 Not used
Bit0 CIS0: COS 0 INT Status
1: COS assert
0: COS not assert
Bit1 CIS1: COS 1 INT Status
1: COS assert
0: COS not assert
Bit2 CIS2: COS 2 INT Status
1: COS assert
0: COS not assert
Bi3 CIS3: COS 3 INT Status
1: COS assert
0: COS not assert
Bit15 COS0E: COS 0 Interrupt enable status
1: Enabled
0: Disabled