Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 308)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 308
The Reset mask Register can disable forwarding of global reset to the reset domains by setting
the corresponding mask bit.
Table 8-84 Reset Mask Register
Address: 0x16 -0x17
Bit Description Default Access
0 Mask GPP Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
1 Mask Broadcom Ethernet Switch Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
2 Mask DMC Base Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
3 Mask DMC 1 Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
4 Mask DMC 2 Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
5 ARTM Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
6 Telecom Clock Device ACS8520 Reset PWR_GOOD: 0 SPP: r/w
IPMC: r/w
7 SRIO Reset PWR_GOOD: 0 SPP: r/w
IPMC: r
15:8 Reserved 0 r