Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 363)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 363
8.2.3.12.1 External failure input signals
 Status register (write one to clear)
 Interrupt mask register
 Failover mask register
 Active level control (active-high/low)
 Edge/level control (fault signal is level- or edge triggered)
 "Healthy" signals from other FPGA devices (DMC base, DMC 1, DMC 2 and ARTM) which
contain the same logic for driving their healthy signals.
Figure 8-9 Failover Logic Overview
FPGA
REQ _ CNTR
ENABLE ( PWRGD )
ACTIVE
R / S
R Q
S
NEG _ I
NEG _ O
HEALTH _ O
Backplane Blade 1 Blade 2
HEALTH _ I
FPGA
REQ _ CNTR
ENABLE ( PWRGD )
ACTIVE
R / S
R Q
S
NEG _ I
HEALTH _ I
NEG _ O
HEALTH _ O