Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 433)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 433
1 MdcDirSet RW 0b1: MdcAsOutputSet, Mdc line
(Clock) of Mdio bus is driven by Dsp
Fpga
0b0: MdcAsInputSet, Mdc line (Clock)
of I2c is not driven by Dsp Fpga, thus
data from Phy can be read 0b0 X X
0 MdcValIfOutSet RW 0b1: MdcValSetHigh, Mdc line (Clock)
of I2c is driven high by Dsp Fpga if
direction is set as output
0b0: MdcValSetLow, Mdc line (Clock)
of Mdio bus is driven low by Dsp Fpga
if direction is set as output 0b0 X X
Table 8-228 MDIO Bit Bang Register (continued)
Bit Acronym Type Description Default Pwr Soft