Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 331)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 331
2 Software Fault 2 enable:
0: Event disabled
1: Event enabled. 0 SPP: r/w
3 Software Fault 3 enable:
0: Event disabled
1: Event enabled. 0 SPP: r/w
4 Software Fault 4 enable:
0: Event disabled
1: Event enabled. 0 SPP: r/w
5 DMC Base Fault enable
0: Event disabled
1: Event enabled. Ext. SPP: r/w
6 DMC 1 Fault enable
0: Event disabled
1: Event enabled. Ext. SPP: r/w
7 DMC 2 Fault enable
0: Event disabled
1: Event enabled. Ext. SPP: r/w
8 RTM Fault enable
0: Event disabled
1: Event enabled. Ext. SPP: r/w
15:9 Reserved 0 r
Table 8-134 Fault Event Enable Register (continued)
Address Offset: 0x84 - 0x85
Bit Description Default Access