Motorola MVME1X7P - Manual (Page 202)

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PCCchip2
3
MPU Channel Attention access is used to cause the 82596CA to begin
executing memory resident Command blocks. To execute an MPU
Channel Attention, the Local Bus bus master performs a simple read or
write to address $FFF46004.
MC68040-Bus Master Support for 82596CA
The 82596CA has DMA capability with an Intel i486-bus interface. When
it is the local bus master, external hardware is needed to convert its bus
cycles into MC68040-bus cycles. When the 82596CA has local bus
mastership, the PCCchip2 drives the following Local Bus (MC68040-bus)
signal lines:
❏ Snoop Control SC1-SC0. (With the value programmed into the
LAN Interrupt Control Register.) (Only SC1 is used on the
MVME177.)
❏ Transfer Types TT1-TT0. (With the value of %00.)
❏ Transfer Modifiers TM2-TM0. (With the value of %101.)
❏ Transfer Acknowledge (TA*) if Transfer Error Acknowledge
(TEA*) is detected.
LANC Bus Error
The 82596CA does not provide a way to terminate a bus cycle with an
error indication. The interface to the 82596CA on the Single-Board
Computers provides several ways of processing bus errors that occur while
the 82596CA is local bus master. These options are controlled by registers
in the VMEchip2 and the PCCchip2.
The GPIO2 signal on the VMEchip2 LCSR (address $FFF40088) controls
how the 82596CA interface logic responds to bus errors. If the GPIO2
signal is programmed as an input (reset state) or programmed as an output
and set high, bus errors are processed in the following way.
The 82596CA interface logic monitors all bus cycles initiated by the
82596CA, and if a bus error is indicated (TEA* = 0 and TA* = 1), the Back
Off signal (BOFF*) to the 82596CA is asserted to keep the 82596CA off
the local bus and prevent it from transmitting bad data or corrupting local