Motorola MVME1X7P - Manual (Page 250)

4-2 Computer Group Literature Center Web Site
MCECC Functions
4
Features
MCECC functions now implemented on the Petra chip include:
Table 4-1. MCECC Functions on the Petra ASIC
Function Features
Memory Control 2-1-1-1 memory accesses (sustained) for burst writes
4-1-1-1 memory accesses (sustained) for burst reads (5-1-1-1 with BERR
on or when FSTRD is cleared)
Support for byte, two-byte, four-byte, and cache line read or write transfers
Programmable base address for DRAM
Built-in refresh timer and refresh controller
Programmable-period automatic scrub operation
Error Handling ECC Single-Bit Error Detect and Correct
Software-enabled Interrupt on Single-Bit Error
Double-Bit Error Detect
Software-programmable Bus Error and/or Interrupt on double-bit error