Motorola MVME1X7P - Manual (Page 203)

Functional Description
http://www.motorola.com/computer/literature 3-5
3
memory. The LANC Error Status Register in the PCCchip2 is updated and
a LANC bus error interrupt is generated if it is enabled in the PCCchip2.
The Back Off signal remains asserted until the 82596CA is reset via a port
reset command. After the 82596CA is reset, pending operations must be
restarted.
If the GPIO2 signal is programmed as an output and set low, bus errors are
processed in the following way. The 82596CA interface logic monitors all
bus cycles initiated by the 82596CA, and if a bus error is indicated (TEA*
= 0 and TA* = 1), the interface logic asserts the TA* signal to terminate
the bus cycle. The LANC Error Status Register in the PCCchip2 is updated
and a LANC bus error interrupt is generated if it is enabled in the
PCCchip2. In this case the 82596CA continues to operate and because the
cycle was terminated with an error, the 82596CA may transmit bad data or
corrupt memory.
LANC Interrupt
When the PCCchip2 detects a high level on the INT signal from the
82596CA, if such interrupts are enabled, it generates an interrupt to the
MPU.
If the C040 bit is set, the interrupt request goes to the MPU via the EIPL*
pins at the level that is programmed for LANC interrupts in the LANC
Interrupt Control Register.
If the C040 bit is cleared, the interrupt goes to the MPU via the INT pin (if
the level that is programmed for LANC interrupts in the LANC Interrupt
Control Register is higher than the level set in the Interrupt Mask Level
Register).
When the MPU acknowledges the LANC interrupt, the PCCchip2
responds with the vector that corresponds to LANC interrupts.