Motorola MVME1X7P - Manual (Page 29)

Introduction
http://www.motorola.com/computer/literature 1-3
1
Features
The “Petra” ASIC supplants the MCECC memory controller ASIC on
MVME1X7P boards, performing the memory control functions previously
carried out by the MCECC chip: It supplies the programmable interface for
the ECC-protected 16/32/64/128MB DRAM emulation.
The following table summarizes the features of the MVME167P and
MVME177P single-board computers.
Table 1-1. MVME1X7P Features Summary
Feature MVME167P MVME177P
Processor 25/33MHz 32-bit MC68040
microprocessor 50/60MHz 32-bit MC68060
microprocessor
DRAM 16/32/64/128MB synchronous DRAM (SDRAM). Configurable to emulate
4/8/16/32/64/128MB ECC-protected DRAM
MVME1X7P boards use SDRAM (Synchronous DRAM) in place of DRAM.
Up to 64MB SDRAM is available on MVME167P boards; up to 128MB is
available on MVME177P boards.
SRAM 128KB SRAM with battery backup
EPROM Four 44-pin JEDEC standard PLCC
EPROM sockets Two 44-pin JEDEC standard PLCC
EPROM sockets
Flash Not available Four Intel 28F008SA Flash memory
devices with optional write protection
NVRAM and
RTC 8K by 8 Non-Volatile RAM (NVRAM) and Real-Time Clock (RTC) with
battery backup and watchdog function (SGS-Thomson M48T58)
Timers Four 32-bit tick timers and watchdog timer in Petra ASIC
Two 32-bit tick timers and watchdog timer in VMEchip2 ASIC
Software
Interrupts Eight software interrupts (including those in the VMEchip2 ASIC)
I/O Four EIA-232-D configurable serial ports via P2 and transition module
Parallel (printer) interface via P2 and transition module
SCSI interface with DMA via P2 or LCP2 adapter board
Ethernet transceiver interface via DB15 connector on transition module