Motorola MVME1X7P - Manual (Page 75)

Cache Coherency (MVME167P)
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Periodic Tick Timer 1 interrupts now occur, so you need an interrupt
handler. Section 3 gives the details, as follows.
3. Set up an interrupt handler routine:
Cache Coherency (MVME167P)
The MVME167P’s MC68040 processor has the ability to watch Local Bus
cycles executed by other Local Bus masters such as the SCSI DMA
controller, the LAN controller, the VMEchip2 DMA controller, and the
VMEbus-to-Local-Bus controller. This bus snooping capability is
described in the M68040 Microprocessors User’s Manual sections on
Cache Coherency and Bus Snooping Operation.
When snooping is enabled, the MC68040 MPU can source data and
invalidate cache entries as required by the current cycle. The MPU cannot
watch VMEbus cycles that do not access the Local Bus. Software must
Step Action and Reference
Your interrupt handler should include the following features.
1 Be sure the MC680x0 Vector Base register is set up. Set the proper MC680x0
exception vector location so the processor vectors to your interrupt handler location.
You can determine the proper exception vector location to set from the MC680x0
Vector Base register, the VMEchip2 Base register, and Table 2-4, Local Bus
Interrupter Summary in Chapter 2, from which you can determine the actual interrupt
vector given on a Tick Timer 1 interrupt. Lower the MC680x0 mask so the interrupt
level you programmed is accepted. The interrupt handler itself should include the
following (steps 2 through 5).
2 Confirm that the Tick Timer 1 interrupt occurred, by reading the status of bit 24 in the
Interrupter Status register at $FFF40068. A high indicates an interrupt present.
3 Clear the Tick Timer 1 interrupt by writing a 1 to bit 24 of the Interrupt Clear register at
$FFF40074.
4 Increment a software counter to keep track of the number of interrupts, if desired.
Output a character or some other action (such as toggling the
FAIL LED) on an
appropriate count, such as 1000.
5 Return from exception.