Motorola MVME1X7P - Manual (Page 205)

Functional Description
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General Purpose I/O Pin
The General Purpose I/O pin can be used as an input pin, as an output pin,
or as both. The PCCchip2 has a status bit that reflects the state of the pin.
The PCCchip2 also has a control bit that allows it to drive the pin, and
another control bit that controls the level that is driven.
The input can be configured to generate an interrupt to the MPU in any of
the following programmable conditions: high level, low level, high-to-low
transition, or low-to-high transition.
CD2401 SCC Interface
The PCCchip2 provides the required logic to interface the CL-CD2401
(SCC) Intelligent MultiProtocol Peripheral to the MC68040-compatible
Local Bus. The interface logic consists of a local master interface, a local
slave interface, a CD2401 Host interface, a CD2401 DMA interface, a
CD2401 interrupt handler, and a Local Bus requester.
The base address for the CL-CD2401 is $FFF45000. It has 8- and 16-bit
registers only. Consequently it does not respond when accessed with a size
of 4 bytes (SIZ1,0 = %00) or with a size of 16 bytes (SIZ1,0 = %11).
There are three interrupts sources from the SCC: receive interrupt, transmit
interrupt, and modem interrupt. The PCCchip2 provides the ability to
individually program the priority level of each of these interrupt sources.
When the C040 bit is set, these interrupts are sent to the MPU via the
EIPL* pins (at the programmed level).
When the C040 bit is cleared, they are sent to the MPU via the INT pin.
(The INT pin is only asserted if the programmed level of the interrupt
source is higher than the level programmed into the Interrupt Mask Level
Register.)
There are two interrupt acknowledge modes supported by the PCCchip2
for the SCC: auto vector and direct. In auto vector mode, the PCCchip2
supplies the interrupt vector to the MPU. (No interrupt acknowledge cycle
is seen by the CD2401.) In direct mode, the SCC supplies the vector to the
MPU. (The PCCchip2 passes the interrupt acknowledge cycle on through