Intel NetStructure MPCBL0001 - Manual (Page 72)

72 Technical Product Specification
Order #273817
Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Contents
The implementation details are as below:
1. CMM sends a frucontrol=3 command to IPMC initiating a diagnostic interrupt.
2. When the IPMC receives frucontrol=3, it asserts the NMI signal to the CPU via the GPIO pins
connected to the H_NMI pin.
3.16 Serial Port Buffering Overview
Serial port buffering occurs when the IPMC on the blade reads and buffers characters coming from
a serial console port on the Super I/O chipset used in the SBC. This serial data could be from the
operating system, such as Linux, running on the blade. This data could then be read back via IPMI
commands via the shelf manager so that an operator can see a “snapshot” of the last few lines of
text output by the blade before it crashed or otherwise stopped working.
The buffer in the IPMC used to store the serial information is 2048 (0800h) bytes. It is big enough
to hold an 80x25 screen of data with a CR/LF pair at the end of 24 lines. When the buffer fills, it
wraps around so that the oldest data is overwritten by newer data.
The board uses a Super I/O controller that has two RS232 serial ports. The first port (COM1) is
routed to the front panel of the blade and has no connectivity to the IPMC. The second serial port
(COM2) is only connected directly to a serial port on the IPMC. Any data that needs to be buffered,
therefore, needs to be directed out the second serial port (COM2). Data coming from COM1 cannot
be monitored or buffered by the IPMC.
This feature also provides the capability to filter out certain ANSI escape sequences coming into
the serial port. This is so the buffer does not fill with escape sequences that provide no meaningful
content. This is particularly true of messages output by BIOS during startup. If only Linux output is
desired, then the filtering option is probably not needed.
When enabled, the filter prevents the buffering of the following escape sequences:
Figure 12. Diagnostic Interrupt Command Implementation
CPU
(H_NMI)
IPMC CMM
IPMB Interface GPIO
Cmmset –l bladex –d frucontrol –v 3
Asserts NMI signal
1
2