Intel NetStructure MPCBL0001 - Manual (Page 95)

Technical Product Specification 95
Order #273817
Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Contents
Addressing
5
5.1 Configuration Registers
5.1.1 Configuration Address Register MCH CONFIG_ADDRESS
I/O Address: 0x0CF8 Accessed as a Dword
Default Value: 0x00000000
Access: Read/Write
Size: 32 bits
CONFIG_ADDRESS is a 32-bit I/O register that can be accessed only as a Dword. A byte or word
reference passes through the Configuration Address Register and hub link interface HI_A onto the
PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent PCI configuration access
is intended. This register is defined by the PCI Bus Specification.
5.1.2 Configuration Data Register MCH CONFIG_ADDRESS
I/O Address: 0x0CFC
Default Value: 0x0000000
Access: Read/Write
Size: 32 bits
Table 54. Configuration Address Register Bit Assignments
Bit 31 30 24 23 16 15 11 10 8 7 2 1 0
0 R 0 0 0 0 R Default
Bit Description
31
Configuration Enable (CFGE): When this bit is set to 1, accesses to the PCI configuration space
are enabled. When this bit is reset to 0, accesses to the PCI configuration space are disabled.
30:24 Reserved (These bits are read only and have a value of 0).
23:16 Bus Number: Contains the bus number being targeted by the configuration cycle.
15:11 Device Number: Selects one of the 32 possible devices per bus.
10:8 Function Number: Selects one of eight possible functions within a device.
7:2
Register Number: This field selects one register within a particular bus, device, and function as
specified by the other fields in the Configuration Address Register. This field is mapped to A[7:2]
during HI_A-D configuration cycles.
1:0 Reserved.