Alignment blocks, 3 alignment blocks – Intel NetStructure MPCBL0001 User Manual

Page 86

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Technical Product Specification

Order #273817

Intel NetStructure

MPCBL0001 High Performance Single Board Computer

Contents

P[C]dxp where:

P = Prefix (B=Base Interface [Gigabit Ethernet], F= Fabric Interface [Fibre Channel])

C = Channel (1-2)

d = direction (Tx = Transmit, Rx = Receive)

x = port number (0-1)

Note:

A port is two differential pairs, one Tx and one Rx

p = polarity (+, -)

The BG, DG, FG and HG (G for Ground) columns contain the ground shields for the four columns
of differential pairs. They have been omitted from the pin out tables below for simplification. All
pins in the BG, DG, FG and HG columns are connected to Logic Ground. The used base fabric
(Gigabit Ethernet) channels are shown in light gray while the used extended fabric (Fibre Channel)
ports appear in dark gray.

4.1.3

Alignment Blocks

The MPCBL0001 SBC implements the K1 and K2 alignment blocks at the top of Zone 2 and Zone
3, as required in section 2.4.4 of the PICMG 3.0 Specification. These are identified on the
silkscreen as GP1 and GP2. GP1 provides the PICMG 3.0-mandated keying value of 11, and is
either a Tyco* 1469373 or a Tyco 1469268 component (or equivalent). GP2 has a solid face and is
used to ensure that RTMs with protruding connectors are not plugged into the MPCBL0001 SBC
or vice versa; the component used for this is either a Tyco 1469374 or a Tyco 1469275-2 (or
equivalent).

Table 46.

Data Transport Connector (Zone 2) P23 Pin Assignments

Pin

No Connect

F[2]Tx0+

F[2]Tx0-

F[2]Rx0+

F[2]Rx0-

No Connect

F[1]Tx0+

F[1]Tx0-

F[1]Rx0+

F[1]Rx0-

No Connect

B[1]Tx0+

B[1]Tx0-

B[1]Rx0+

B[1]Rx0-

B[1]Tx1+

B[1]Tx1-

B[1]Rx1+

B[1]Rx1-

B[2]Tx0+

B[2]Tx0-

B[2]Rx0+

B[2]Rx0-

B[2]Tx1+

B[2]Tx1-

B[2]Rx1+

B[2]Rx1-

Reserved

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