Document Outline

• Xilinx System Generator v2.1 for Simulink
  • Introduction
    • Industry and Product Overview
    • System Generator
    • System Level Modeling with System Generator
    • The System Generator Design Flow
    • Arithmetic Data Types
    • Hardware Handshaking
      • Multirate Systems
    • Bit-True and Cycle-True Modeling
      • Automatic Testbench Generation
  • Xilinx Blockset Overview
    • What is a Xilinx Block?
    • Instantiating Xilinx Blocks within a Simulink Model
    • The Block Parameters Dialog Box
    • The Nature of Signals in the Xilinx Blockset
    • Use of Xilinx Smart-IP Cores by the System Generator
      • Licensed Cores
      • Xilinx LogiCORE‘ Versions
    • Common Options in Block Parameters Dialog Box
      • Arithmetic Type
      • Implement with Xilinx Smart-IP‘ Core (if possible)
      • Generate Core
      • Latency
      • Precision
      • Number of Bits
      • Overflow and Quantization
      • Override with Doubles
      • Sample Period
  • Xilinx Blocks
    • Basic Elements
      • System Generator
      • Addressable Shift Register
      • Black Box
      • Concat
      • Constant
      • Convert
      • Counter
      • Delay
      • Down Sample
      • Get Valid Bit
      • Mux
      • Parallel to Serial
      • Register
      • Reinterpret
      • Serial to Parallel
      • Set Valid Bit
      • Slice
      • Sync
      • Up Sample
    • Communication
      • Convolutional Encoder
      • Depuncture
      • Interleaver Deinterleaver
      • Puncture
      • RS Decoder
      • RS Encoder
      • Viterbi Decoder
    • DSP
      • CIC
      • DDS
      • FFT
      • FIR
    • Math
      • Accumulator
      • AddSub
      • CMult
      • Inverter
      • Logical
      • Mult
      • Negate
      • Relational
      • Scale
      • Shift
      • SineCosine
      • Threshold
    • MATLAB I/O
      • Gateway Blocks
      • Enabled Subsystems
      • Gateway In
      • Gateway Out
      • Quantization Error Blocks
      • Display
    • Memory
      • Dual Port RAM
      • FIFO
      • ROM
      • Single Port RAM
    • State Machine
      • Mealy State Machine
      • Moore State Machine
      • Registered Mealy State Machine
      • Registered Moore State Machine
  • System Generator Software Features
    • Using the System Generator installer
      • Uninstalling previous System Generator directories
      • Installed System Generator directory
    • Using Black Boxes
      • A Black Box Example
      • Black Box window
    • Use of mixed language projects
      • Incorporating mixed language black boxes
    • Tips for creating a high performance design
    • Using the System Generator Constraints Files
      • System Clock Period
      • Multicycle Path Constraints
      • IOB Timing and Placement Constraints
      • Example for showing constraints use
      • Important Issues
    • Files automatically created by System Generator
  • Using the Xilinx Software
    • Xilinx ISE 4.1i Project Navigator
      • Opening a System Generator project
      • Customizing your System Generator project
      • Implementing your design
      • Simulating using ModelSim within the Project Navigator
    • Using an EDIF software flow
    • Simulation
      • Compiling your IP
      • Associating ModelSim with ISE 4.1i Project Navigator
    • Xilinx software tools resources
  • Auxiliary Files
    • Demonstration designs
    • Perl scripts