Rockwell Automation 1734-VHSC24 Very High-Speed Counter Modules User Manual - Manual (Page 37)

Publication 1734-UM003B-EN-P - August 2000
Very High-Speed Counter Module Input and Output Data 3-7
Filter Selection (Configuration Word 2)
This byte sets the A/B/Z input filters.
Filter Selection
Decimal Position (Configuration Word 3)
This byte changes the significant digits of the frequency or counter
display.
In the frequency modes (period/rate [5], continuous/rate [6], rate
measurement [7]) for example, a -2 moves the decimal point left 2
places, dividing the frequency value by 100, a +1 moves it right,
multiplying by 10. The firmware checks for placement to be in the
range -4
≤ value ≤ +2. A value outside the range moves the decimal
point to the zero position and asserts the programming error (PE) bit.
Moving the decimal point to the left (negative), allows high
frequencies, commonly present in rate measurement mode, to fit
within a single 16-bit word. Moving the decimal point to the right
(positive), allows low frequencies, commonly present in period and
continuous rate modes, to have resolution displayed to 0.1 Hz and
0.01 Hz. Keep frequencies below 3.2 kHz for 0.1 Hz resolution and
below 320 Hz for 0.01 Hz. Scalars of Z/128, Z/64, Z/32, and Z/16
should not be used when positioning is applied. 0 is the default
setting.
07 06 05 04 03 02 01 00
0 ZF BF AF FS
0 0 0 0 No Filter
0 0 0 1 50 kHz (10 µs + 0 µs/-1.6 µs)
0 0 1 0 5 kHz (100 µs + 0 µs/-13.2 µs)
0 1 0 0 500 Hz (1.0 ms + 0 µs/-125 µs)
1 0 0 0 50 Hz (10 ms + 0 ms/-1.25 ms)
0 A input not filtered
1 A input filtered
0 B input not filtered
1 B input filtered
0 Z input not filtered
1 Z input filtered