Rockwell Automation 1746-HSCE2 Multi-Channel High Speed Counter Module - Manual (Page 105)

Publication 1746-UM002B-EN-P - August 2004
Application Examples 6-13
Ladder File 9 - HSCE2 Initialization Routine
Programming ladder file 9 shows the block transfer function required
to set up the programming blocks in this example.
0000
LES
Less Than (A<B)
Source A
N11:0
140<
Source B
N11:1
140<
DATA_BLOCK_POINTER
N12:10
15
HSCE2_TRNSMIT
N12:0
15
HSCE2_ACK
COP
Copy File
Source #N10:[N11:0]
Dest
#N12:10
Length 8
#BTW_DATA
L
N12:10
15
HSCE2_TRNSMIT
0001
N12:10
15
HSCE2_TRNSMIT
N12:0
15
HSCE2_ACK
U
N12:10
15
HSCE2_TRNSMIT
MEQ
Masked Equal
Source
N12:0
770<
Mask
6000h
8192<
Compare
0
0<
ADD
Add
Source A
N11:0
140<
Source B
10
10<
Dest
N11:0
140<
DATA_BLOCK_POINTER
0002
EQU
Equal
Source A
N11:0
140<
Source B
N11:1
140<
DATA_BLOCK_POINTER
N12:10
15
HSCE2_TRNSMIT
N12:0
15
HSCE2_ACK
COP
Copy File
Source #N10:[N11:0]
Dest
#N12:10
Length 8
#BTW_DATA
L
B3:0
0
HSCE2_INIT_DONE
0003
N12:0
15
HSCE2_ACK
N12:0
13
HSCE2_PERR
N12:0
14
HSCE2_FAULT
L
B3:0
1
HSCE2_ERROR
0004 END
If the blocks have not all been transmitted (block data pointer < max block offset), copy next block to the HSCE2 and set transmit bit
(N12:10/15).
When HSCE2 sets its acknowledge bit (N12:0/15), reset the module handshaking bit (N12:10/15) and check HSCE2 programming
error bit (N12:0/13). If no error bits are ON, increment the block counter to permit the next block move to start.
When the last block is completed (block data offset = max block offset), copy the Counter Control Block to the HSCE2.
Note: The Counter Control Block does not require a 0-1 positive transition of the transmit bit to operate.
If BTR returns a programming error bit, set HSCE2 error bit (B3/3).