Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 12)

12 UG029, September 6, 2013
Interface Signal List
ref_clk
reset_ff_rx_clk_n[2:0]
reset_ff_tx_clk_n[2:0]
reset_n
reset_ref_clk_n
align_done[2:0]
block_lock[11:0]
hi_ber[11:0]
loc_fault[11:0]
rem_fault[11:0]
pma_{11:0}_pd[1:0]
pma_rx_cdr_lck2dat[11:0]
pma_rx_iddq_n[11:0]
pma_rxready[11:0]
pma_rxstat[11:0]
pma_sig_detect[11:0]
pma_synth_iddq_n[11:0]
pma_synthready[11:0]
pma_synthestat[11:0]
pma_tx_iddq_n[11:0]
pma_txready[11:0]
pma_txstat[11:0]
serdes_aprobe[11:0]
serdes_ck_ref_m[11:0]
serdes_ck_ref_p[11:0]
serdes_rx_m[11:0]
serdes_rx_p[11:0]
serdes_tx_m[11:0]
serdes_tx_p[11:0]
i_sbus_sw_rst
sbus_clk
reg_ts_avail[11:0]
reset_sbus_clk_n
i_sbus_req
i_sbus_data[1:0]
o_sbus_data[1:0]
o_sbus_ack
pma_{11:0}_i_sbus_req
pma_{11:0}_i_sbus_data[1:0]
pma_{11:0}_o_sbus_data[1:0]
pma_{11:0}_o_sbus_ack
pma{11:0}_pd
Fabric Transmit FIFO Interface
Fabric Receive FIFO Interface
Priority Flow Control
Transmitted Frame Status
Auto-Negotiation Control & Status
Global Signals
MAC/PCS Status
PMA TX/RX Interface
FPGA SerDes Off-Chip I/O pins
MAC & PMA Serial Control Bus
Time Stamp Timer
sys_clk
ff_clk[2:0]
ff_tx_data[767:0]
ff_tx_wren[11:0]
ff_tx_sop[11:0]
ff_tx_eop[11:0]
ff_tx_mod[71:0]
ff_tx_err[11:0]
ff_tx_crc[11:0]
ff_tx_rdy[11:0]
ff_tx_ovr[11:0]
ff_tx_id[3:0]
ff_tx_ts_frm
ff_tx_preamble_val
ff_tx_preamble[55:0]
ff_rx_rdy[11:0]
ff_rx_data[767:0]
ff_rx_dval[11:0]
ff_rx_sop[11:0]
ff_rx_eop[11:0]
ff_rx_mod[71:0]
ff_rx_err[11:0]
ff_rx_vlan[23:0]
ff_rx_afull[11:0]
ff_rx_err_stat[23:0]
ff_rx_ts[31:0]
ff_rx_preamble_val
ff_rx_preamble[55:0]
pfc_mode[11:0]
ff_tx_pfc_xoff{11:0}[7:0]
ff_tx_pfc_ack[11:0]
ff_rx_pfc_xoff{11:0}[7:0]
tx_ts_val
tx_ts_id[3:0]
tx_ts[31:0]
an_ena[11:0]
an_int[11:0]
an_done[11:0]
frc_in[31:0]
ts_clk
reset_ts_clk_n
Figure 2: Interface Signal List