Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 79)

UG029, September 6, 2013 79
2 08 VLAN_TPID_2 RW
15:0: VLAN Tag TPID 2.
Bits 31:16 are unused and always set
to ‘0’.
0x8100
3 0C VLAN_TPID_3 RW
15:0: VLAN Tag TPID 3.
Bits 31:16 are unused and always set
to ‘0’.
0x8100
4 10 VLAN_TPID_4 RW
15:0: VLAN Tag TPID 4.
Bits 31:16 are unused and always set
to ‘0’.
0x8100
5 14 VLAN_TPID_5 RW
15:0: VLAN Tag TPID 5.
Bits 31:16 are unused and always set
to ‘0’.
0x8100
6 18 VLAN_TPID_6 RW
15:0: VLAN Tag TPID 6.
Bits 31:16 are unused and always set
to ‘0’.
0x8100
7 1C VLAN_TPID_7 RW
15:0: VLAN Tag TPID 7.
Bits 31:16 are unused and always set
to ‘0’.
0x8100
Channelized PCS Registers
The Channelized PCS Registers are located on pages 16 through 27. Each segment has its own
set of PCS configuration, control and status registers. The register map of each register set is
identical and shown below.
The following register map shows a 32-Bit register implementation. The address is given in
steps of 4 to indicate the 32-bit alignment of the register space. All PCS registers are only 16-
bit wide (15:0). Write accesses to the upper 16-bit (31:16) are ignored, and read always return
0 for these.
Bit 0 is the least significant bit and all registers are initialized to zero upon reset except when
stated otherwise.
The following register and bit types are used:

RW: Read/write register. Unused bits should be written with 0 and ignored on read.

RO: Read only, write has no effect.

WO: Write only, returns all zero on read.

ROR: Read only and Reset. The value is reset to zero after reading the register.

LH: Latch high. Bit stays 1 if event occurred. Latch is cleared after reading the register.

LL: Latch low. Bit stays 0 if event occurred. Latch is cleared after reading the register.

SC: Self-clearing.

NR: Non Roll-over.
Reserved bits or registers default to 0 and are read-only if not stated otherwise.