Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 71)

UG029, September 6, 2013 71
10G MAC SGMII PCS Register Map
When operating in 10G mode of operation, the 10G MAC can implement a configurable
10/100/1000 SGMII/1000Base-X PCS layer instead of the normal XGMII/10GBase-R PCS layer
to allow operations below 10Gbps (See 0 page 71 for further description).
The following registers are accessible to control the SGMII PCS operation. The register set is
found in the MAC register space from offset 0x300 onwards for each segment individually.
The registers only have 16-bit of relevant data in the lower 16 bits of each 32-bit word. The
upper 16 bits are ignored. The implementation follows the IEEE 802.3 Clause 22 register set
layout.
1000Base-X / SGMII PCS
SGMII PCS Register Map
Reg#
Addr
(hex)
Register Name Typ Description
Reset
Value
0 300 CONTROL RW
Control Register. Used to enable / disable
functions in the PCS and to initiate
commands such as reset.
See Table 37
– (SGMII PCS) CONTROL
Register Description on page 73
0x1140
1 304 STATUS RO
Status Register. Provides information on
the operation of the PCS.
See Table 38
– (SGMII) PCS STATUS
Register Description on page 73
0x0009
2 308
PHY_IDENTIFIER
RO
PHY Identification Register. Read only
register programmed with a custom value.
0x4950
3 30c RO
PHY Identification Register. Read only
register programmed with a custom value.
0x4d54
4 310 DEV_ABILITY RW
Device ability register advertised to the
link partner during the Auto-negotiation
process.
Bits 15, 13:0 are programmable. Bit 14 is
not relevant and should be written with 0
always.
The bit definitions are shown in Table 39
– (SGMII PCS)
DEVICE/PARTNER_ABILITY Register
Description - 1000Base-X mode on page
74
Note: The register value is typically not
relevant in SGMII mode and can be left at
its default (must not be 0 in any mode). A
SGMII PHY normally does not interpret
this value. Please check with the PHY
vendor documentation if any value needs
to be programmed for SGMII auto-
negotiation.
0x01a0