Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 59)

UG029, September 6, 2013 59
Registers
MAC & PCS Configuration Registers
MAC & PCS Register Overview
The MAC & PCS register address space is divided into 32 register pages with 256 registers
each. The register pages are addressed by putting the page number/address on the serial bus
interface pins. (
i_sbus_req,i_sbus_data[1:0],o_sbus_data[1:0],o_sbus_ack) .
The following register map shows the assignment of the different register pages.
The Address in the table below is given in byte offsets as it would typically appear in a
memory mapped address space, however the registers are accessible in steps of 32 bit only
(i.e. address offset 0x04 accesses register 1, 0x08 accesses register 2, ...).
Table 30 – Core Register Map – Channelized MAC Registers
Address Page# Description 10G 40G 100G
0x0000 0
Segment 0 MAC Configuration, Control
and Status Registers
See
Channelized MAC Registers on page
61.
yes
yes,
SEG0
yes,
SEG0
0x0400 1
Segment 1 MAC Configuration, Control
and Status Registers
yes no no
0x0800 2
Segment 2 MAC Configuration, Control
and Status Registers
yes no no
0x0c00 3
Segment 3 MAC Configuration, Control
and Status Registers
yes no no
0x1000 4
Segment 4 MAC Configuration, Control
and Status Registers
yes
yes,
SEG4
no
0x1400 5
Segment 5 MAC Configuration, Control
and Status Registers
yes no no
0x1800 6
Segment 6 MAC Configuration, Control
and Status Registers
yes no no
0x1c00 7
Segment 7 MAC Configuration, Control
and Status Registers
yes no no
0x2000 8
Segment 8 MAC Configuration, Control
and Status Registers
yes
yes,
SEG8
no
0x2400 9
Segment 9 MAC Configuration, Control
and Status Registers
yes no no
0x2800 10
Segment 10 MAC Configuration,
Control and Status Registers
yes no no
0x2c00 11
Segment 11 MAC Configuration,
Control and Status Registers
yes no no