Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 41)

UG029, September 6, 2013 41
When an Ethernet frame is received with an error, the frame is transmitted to the user
application with the frame error signal (ff_rx_err[0]) asserted with the last word of the
frame.
In addition, the MAC Core provides a 24-Bit error status word (ff_rx_err_stat[23:0])
that gives an indication on the error source (see section "" for details). Note that the receive
status ff_rx_err_stat[23:0] can only be mapped to any segment of FIFO group 0 (10G:
SEG0-3, 40G: SEG0, 100G: SEG0).
sys_clk
ff_rx_data[511:0]
ff_rx_sop[0]
ff_rx_eop[0]
ff_rx_mod[5:0]
ff_rx_err[0]
ff_rx_vlan[1:0]
ff_rx_err_stat[23:0]
ff_rx_dval[0]
ff_rx_rdy[0]
Figure 17: FIFO Receive Interface – Frame Transfer with Error
The user may pause the output of the receive FIFO by deasserting the ff_rx_rdy[0] signal.
The ff_rx_rdy[0] indicates that the user circuit has consumed the current data word at the
output of the receive FIFO. The following figure illustrates how the user may pause the data
output from the receive FIFO.