Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 49)

UG029, September 6, 2013 49
Serial Bus Interface
Overview
The Serial Bus (SBUS) Slave module is a low pin count serial interface for data transfer
between the Hard IP and the FPGA Fabric. There are 13 independent SBUS interfaces. One
32-bit interface for the 10/40/100G Ethernet MAC/PCS and an additional 12 8-bit interfaces for
the 12 PHY SerDes channels. The Serial bus protocol is decoded and converted into a parallel
register interface called P1 port to provide access to registers by the fabric/embedded IP.
Any transfer on the SBUS is initiated by asserting REQ. The first bit on the input data bus
indicates whether it is a read or a write operation. Refer to the READ/WRITE Operation for
more details. Any subsequent READ or WRITE operation should be initiated only after the
current operation is completed once o_sbus_ack is asserted by the SBUS Slave interface.
Port List
The port definitions for SBUS Slave Block are defined in the table below.
Port Direction Description
reset_sbus_clk Input Asynchronous reset
sbus_clk Input
Reference clock for the serial
and parallel interface –
p1_ctl_clk
i_sbus_req Input
Request signal for starting a
read or write transaction on
SBUS.
i_sbus_data[1:0] Input
Input serial data of SBUS
interface. The data width can be
2bits or 1bits.
o_sbus_data[1:0] Output
Output serial data of SBUS
interface. The data width can be
2bits or 1bits.
o_sbus_ack Output
Acknowledgement signal for
read and write operation
complete on SBUS interface.
Table 26 – Port definition for SBUS Module
Read Operation
For starting a read operation the i_sbus_req is asserted for 9 cycles with the first data bit of
i_sbus_data[0] being de-asserted. The read address which is 17bit long is sent next starting
with the least significant bit.
The SBUS slave decodes the read operation and responds. Then it asserts the o_sbus_ack for
16 cycles for the case of the 32-bit data bus of the Ethernet block interface and 4 cycles for the
case of a 8-bit data of the SerDes SBUS interfaces..
The figures below show the timing diagram for operation mode on each of the 32-bit and 8-
bit SBUS interfaces.