Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 35)

UG029, September 6, 2013 35
Table 19 – 10G Transmit/Receive FIFO Interface Word Modulo Definition
ff_tx_mod[5:0]
ff_rx_mod[5:0]
Valid Bytes
000000 ff_tx_data[63:0], ff_rx_data[63:0]
000001 ff_tx_data[7:0], ff_rx_data[7:0]
000010 ff_tx_data[15:0], ff_rx_data[15:0]
000011 ff_tx_data[23:0], ff_rx_data[23:0]
000100 ff_tx_data[31:0], ff_rx_data[31:0]
000101 ff_tx_data[39:0], ff_rx_data[39:0]
000110 ff_tx_data[47:0], ff_rx_data[47:0]
000111 ff_tx_data[55:0], ff_rx_data[55:0]
001000 - 111111 invalid
Note: Note: Only datapath bit assignment for segment 0 is shown. The bit assignments for segments
1 to 11 are defined accordingly.
The user application does not have to manage the Ethernet frame formats in full detail. It
needs to provide and will receive an Ethernet frame with the following structure:

Ethernet MAC Destination Address

Ethernet MAC Source Address

Optional 802.1q VLAN Tag (VLAN Type and VLAN Info fields)

Ethernet Length / Type field

Payload
Frames on the FIFO interface do not contain preamble and SFD fields, which are inserted and
discarded by the MAC on transmit and receive, respectively.
On receive, CRC can be stripped or passed through transparently. The Payload length must
not exceed the value programmed in the Core configuration register FRM_LENGTH.
On transmit, padding and CRC can be provided by the user application, or appended
automatically by the MAC independent for each frame. No size restrictions apply.
Note: On transmit, if the Core configuration register TX_ADDR_INS is set to 1, the byte 6 to 11 of
each frame can be set to any value since the MAC will overwrite the bytes with the MAC address
programmed in registers MAC_ADDR_0 and MAC_ADDR_1.