Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 37)

UG029, September 6, 2013 37
FIFO Interface Transmit Operation
The application layer drives data and controls based on the configuration mode. Note that for
improved readability, the following figures only show data transfers for segment 0 in 100G
mode of operation. For all other segments in other configuration modes, the corresponding
signals need to be defined accordingly.
The user application asserts the FIFO write enable signal (ff_tx_wren[0]) to transfer data
to the MAC Core Transmit FIFO segment 0.
The user application must send the first word of a frame with the start of frame signal
(ff_tx_sop[0]) and the last word with the end of frame signal (ff_tx_eop[0]) asserted.
With the last word, a word modulo signal (ff_tx_mod[5:0]) must indicate which portion
of the bus is valid. Also the error signal (ff_tx_err[0]) and CRC append signal
(ff_tx_crc[0]) must be valid.
In case of a FIFO overflow, the Core asserts an overflow indication signal (ff_tx_ovr[0])
as long as the overflow condition persists.
Optionally a user specific preamble can be provided on ff_tx_preamble[55:0]. To
indicate a valid preamble, ff_tx_preamble_val should be asserted together with
ff_tx_sop. Note that the user defined preamble signals can only be mapped to any
segment of FIFO group 0 (10G: SEG0-3, 40G: SEG0, 100G: SEG0). For all other segments, a
user defined preamble can be specified through the control register interface.
sys_clk
ff_tx_wren[0]
ff_tx_data[511:0]
ff_tx_mod[5:0]
ff_tx_sop[0]
ff_tx_eop[0]
ff_tx_err[0]
ff_tx_preamble_val
ff_tx_preamble[55:0]
Figure 11: FIFO Transmit Interface – Single Frame Transfer
The user application can pause a frame transfer by de-asserting the data write enable signal
(ff_tx_wren[0]) for one or multiple clock cycles. The data transfer stops immediately
when ff_tx_wren[0] is de-asserted. The transfer immediately restarts when the user
application re-asserts ff_tx_wren[0].