Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 34)

34 UG029, September 6, 2013
000001
ff_tx_data[7:0)
ff_rx_data[7:0)
000010
ff_tx_data[15:0]
ff_rx_data[15:0]
000011
ff_tx_data[23:0]
ff_rx_data[23:0]
000100
ff_tx_data[31:0]
ff_rx_data[31:0]
… …
111110
ff_tx_data[495:0]
ff_rx_data[495:0]
111111
ff_tx_data[503:0]
ff_rx_data]503:0]
Table 18 – 40G Transmit/Receive FIFO Interface Word Modulo Definition
ff_tx_mod[5:0]
ff_rx_mod[5:0]
Valid Bytes
000000 ff_tx_data[255:0], ff_rx_data[255:0]
000001 ff_tx_data[7:0], ff_rx_data[7:0]
000010 ff_tx_data[15:0], ff_rx_data[15:0]
000011 ff_tx_data[23:0], ff_rx_data[23:0]
000100 ff_tx_data[31:0], ff_rx_data[31:0]
… …
011110 ff_tx_data[239:0], ff_rx_data[239:0]
011111 ff_tx_data[247:0], ff_rx_data[247:0]
100000 - 111111 invalid
Note: Only datapath bit assignment for segment 0 is shown. The bit assignments for segments 4 and
8 are defined accordingly.