Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 24)

24 UG029, September 6, 2013
FPGA Fabric Interface
The fabric interface is the primary interface for the user to connect his design to the 10/40/100
Gigabit Ethernet core. The other side of the core is the dedicated PHY SerDes interface.
The user accesses the Ethernet core via asynchronous transmit and receive FIFO’s. These
FIFO’s have programmable watermarks that are configured by the user. All transfers to/from
the user application are handled independently of the Core operation, and the Core provides
a simple interface to user applications based on a FIFO almost-full flag.
PHY Interface
The Physical Interface (PHY) side of the core is hardwired to specific external SerDes I/O
pins. These pin locations will vary with device and package options, so refer to the datasheet
for your device for these locations. The PHY interface is highly configurable with complex
interactions between configuration registers. The Achronix IP wizard will manage these
configuration options for you. However a small subset of these configuration registers will
be exposed to the user. Refer to the detailed specification on internal PHY PMA registers
later in this document. Each of the twelve PHY channels has a dedicated serial bus for
configuring registers.
Interfacing the Ethernet Core to the FPGA Fabric
Data
The data connections are labeled (ff_tx_* & ff_rx_*). In order to support any packet size, the
transmit and receive interface clocks have to run faster than the nominal required clock
frequency (100Gbps/512b = 195.31 MHz). In 100G mode of operation, worst case is 65-byte
packets, which require two 64-byte words at the user interface to the Ethernet block.
Therefore, for 100G mode, the minimum required transmit/receive interface clock rate is 295
MHz. In the 10G and 40G modes that have narrower interfaces per lane, the data packs more
efficiently, so the required transmit/receive clock rates are lower at 155 MHz. and 177 MHz.
each. There is a simple flow control interface to user application based on a FIFO flag
scheme.
Serial Bus Interface
All internal registers for in the Ethernet core are configurable though a series of 13 serial bus
interfaces. There is one for each for the 12 SERDES channels and one for the MAC/PCS core
itself.
Simulation
In addition to synthesis and place and route functions, the Achronix software flow also
supports various stages of simulation.