Altera Arria II GX FPGA Development Board - Manual (Page 10)

2–2 Chapter 2: Board Components
Board Overview
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Board Overview
This section provides an overview of the Arria II GX FPGA development board,
including an annotated board image and component descriptions.
Figure 2–1
provides an overview of the development board features.
Table 2–1 describes the components and lists their corresponding board references.
Figure 2–1. Overview of the Arria II GX FPGA Development Board Features
Clock Input
SMA
Connector
(J10, J11)
Max II Reset Push-Button Switch (PB4)
General User
Push-buttons
Switches
(PB1, PB2)
Flash x16
Memory (U23)
Board
Settings
DIP Switch
(SW4)
PCI
Express
Edge
Connector
(J14)
DDR3 x16 (U13)
DC Input Jack (J4)
Arria II GX
FPGA
(U19)
Character LCD (J3)
CPU Reset Push-button Switch (PB3)
Power Switch (SW1)
User DIP Switch (SW2)
User LEDs (D7-D10)
MAX II
CPLD
EPM2210
System
Controller
(U32)
Clock
Output
SMA
Connector
(J12)
HSMC Port B (J1) HSMC Port A (J2)
Configuration LEDs (D11-D16)
Load Image (PB5), Image Select Push-button Switch (PB6)
DDR2 SODIMM
(J7)
JTAG Connector
(J5)
USB Type-B
Connector (J6)
Gigabit Ethernet
Port (J8)
JTAG Chain
Header (J9)
Fan Power (J13)
SSRAM x36
Memory (U22)
PCI
Express
Mode
Set
(SW3)
PCI
Express
Mode
Status
(D24-D26)
Table 2–1. Arria II GX FPGA Development Board Components (Part 1 of 3)
Board Reference Type Description
Featured Devices
U19 FPGA EP2AGX125EF35, 1152-pin FBGA.
U32 CPLD EPM2210F256, 256-pin FBGA.
Configuration, Status, and Setup Elements
J6 USB type-B connector Connects to the computer to enable embedded USB-Blaster JTAG.
J9 JTAG chain header Jumper shunts which enables and disables devices in the JTAG chain.
SW4 Board settings DIP switch
Controls the MAX II CPLD EPM2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up.
J5 JTAG connector Disables the embedded blaster (for use with external USB-Blasters).
SW3 PCI Express DIP switch
Controls the PCI Express lane width by connecting prsnt pins
together on the PCI Express edge connector.
D14 Configuration done LED Illuminates when the FPGA is configured.