Altera Arria II GX FPGA Development Board - Manual (Page 56)

2–48 Chapter 2: Board Components
Memory
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Flash
The flash interface consists of a single synchronous flash memory device, providing
64 Mbyte with a 16-bit data bus. This device is part of the shared FSM bus which
connects to the flash memory, SRAM, and MAX II CPLD EPM2210 System Controller.
The parameter blocks are 32 K and main blocks are 128 K. The blocks are located at
the bottom of the address space.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps. The write performance is 270 µs for a single word and
310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K main block.
Table 2–46 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Arria II GX device in terms of I/O setting and
direction.
Table 2–46. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board Reference Description
Schematic Signal Name
I/O Standard
Arria II GX Device
Pin Number
U23.A1 Address bus FSM_A1
2.5-V
J3
U23.B1 Address bus FSM_A2 D29
U23.C1 Address bus FSM_A3 J21
U23.D1 Address bus FSM_A4 L13
U23.D2 Address bus FSM_A5 C8
U23.A2 Address bus FSM_A6 N9
U23.C2 Address bus FSM_A7 D20
U23.A3 Address bus FSM_A8 A23
U23.B3 Address bus FSM_A9 B24
U23.C3 Address bus FSM_A10 C24
U23.D3 Address bus FSM_A11 E25
U23.C4 Address bus FSM_A12 F21
U23.A5 Address bus FSM_A13 J19
U23.B5 Address bus FSM_A14 H19
U23.C5 Address bus FSM_A15 K21
U23.D7 Address bus FSM_A16 L21
U23.D8 Address bus FSM_A17 F25
U23.A7 Address bus FSM_A18 F26
U23.B7 Address bus FSM_A19 G23
U23.C7 Address bus FSM_A20 H21
U23.C8 Address bus FSM_A21 M13
U23.A8 Address bus FSM_A22 P7
U23.G1 Address bus FSM_A23 F10
U23.H8 Address bus FSM_A24 R4
U23.B6 Address bus (die select) FSM_A25 K4
U23.F2 Data bus FSM_D0 A19