Altera Arria II GX FPGA Development Board - Manual (Page 39)

Chapter 2: Board Components 2–31
Components and Interfaces
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
10/100/1000 Ethernet
A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection.
The device is an auto-negotiating Ethernet PHY with an RGMII interface to the FPGA.
The MAC function must be provided in the FPGA for typical networking
applications. The Marvell 88E1111 PHY uses 2.5-V and 1.1-V power rails and requires
a 25 MHz reference clock driven from a dedicated oscillator. It interfaces to a HALO
HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Table 2–35 lists the Ethernet PHY interface pin assignments.
Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
10/100/1000 Mbps
Ethernet MAC
Marvell 88E1111
PHY
Device
Transformer RJ45
RGMII Interface
TXD[3:0]
RXD[3:0]
Table 2–35. Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference Description Schematic Signal
Name
I/O Standard
Arria II GX Device
Pin Number
U24.8 RGMII transmit clock ENET_GTX_CLK
2.5-V
D25
U24.23 Management bus interrupt ENET_INTn D18
U24.25 Management bus control ENET_MDC K20
U24.24 Management bus data ENET_MDIO N20
U24.28 Device reset ENET_RESETn M20
U24.2 RGMII receive clock ENET_RX_CLK V6
U24.95 RGMII receive data ENET_RX_D[0] E21
U24.92 RGMII receive data ENET_RX_D[1] E24
U24.93 RGMII receive data ENET_RX_D[2] E22
U24.91 RGMII receive data ENET_RX_D[3] F24
U24.94 RGMII receive control ENET_RX_DV D17
U24.11 RGMII transmit data ENET_TX_D[0] J20
U24.12 RGMII transmit data ENET_TX_D[1] C25
U24.14 RGMII transmit data ENET_TX_D[2] G22
U24.16 RGMII transmit data ENET_TX_D[3] G21
U24.9 RGMII transmit control ENET_TX_EN G20