Altera Arria II GX FPGA Development Board - Manual (Page 12)

2–4 Chapter 2: Board Components
Board Overview
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
PB5
Load image push-button
switch Load image from flash memory to the FGPA based on the
configuration LED setting.
Memory Devices
J7 DDR2 SODIMM
DDR2 x64 SODIMM 200-pin connector and is populated with a
1-Gbyte memory module.
U13 DDR3 x16 memory Independent 16-bit 128-Mbyte DDR3 memory port.
U22 SSRAM x36 memory
Standard synchronous RAM which makes a 36-bit 2-Mbyte SRAM
port.
U23 Flash x16 memory
Synchronous burst mode flash device which provides a 16-bit
64-Mbyte non-volatile memory port.
Communication Ports
J14 PCI Express edge connector Gold-plated edge fingers for up to ×8 signaling in Gen1 mode.
J2 HSMC port A
Provides four transceiver channels and 80 CMOS or 17 LVDS channels
per the HSMC specification.
J1 HSMC port B
Provides four transceiver channels and 78 CMOS channels per the
HSMC specification (only populated when a EP2AGX260 FPGA device
is installed).
J6 USB type-B connector
USB interface for programming the FPGA through embedded
USB-Blaster JTAG via a type-B USB cable.
J8 Gigabit Ethernet
RJ-45 connector which provides a 10/100/1000 Ethernet connection
via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MegaCore function in RGMII mode.
Display Ports
J3 Character LCD
Connector which interfaces to the 16 character × 2 line LCD module
along with two standoffs at MTH7 and MTH8.
Power Supply
J14 PCI Express edge connector
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
J4 DC input jack
Accepts a 14-V – 20-V DC power supply. Do not use this input jack
while the board is plugged into a PCI Express slot.
SW1 Power switch
Switch to power on or off the board when the DC input jack supplies
power.
Table 2–1. Arria II GX FPGA Development Board Components (Part 3 of 3)
Board Reference Type Description