Altera Arria II GX FPGA Development Board - Manual (Page 20)

2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Arria II GX FPGA
development board. The Arria II GX FPGA development board supports the
following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the load image push-button switch
(PB5).
FPGA Programming over Embedded USB-Blaster
The board implements a USB-Blaster using a USB Type-B connector (J6), a FTDI USB
2.0 PHY device (U15), and an Altera MAX IIZ CPLD (U10). This allows the
configuration of the FPGA using a USB cable directly connected between the USB port
on the board (J6) and a USB port of a PC running the Quartus II software. The JTAG
chain is normally mastered by the embedded USB-Blaster found in the MAX
IIZ
CPLD EPM240Z embedded USB-Blaster.
The embedded USB-Blaster automatically disables when an external USB-Blaster is
connected to the JTAG chain.