Altera SDC and TimeQuest API - Manual (Page 78)

2–68 Chapter 2: SDC and TimeQuest API Package and Commands
sta
SDC and TimeQuest API Reference Manual © December 2009 Altera Corporation
check_timing
Usage
check_timing [-append] [-file <name>] [-include <check_list>] [-panel_name <name>]
[-stdout]
Options
-append: If output is sent to a file, this option appends the result to that file.
Otherwise, the file will be overwritten
-file <name>: Sends the results to an ASCII or HTML file. Depending on the extension
-include <check_list>: Checks to perform
-panel_name <name>: Sends the results to the panel and specifies the name of the new
panel
-stdout: Send output to stdout, via messages. You only need to use this option if you
have selected another output format, such as a file, and would also like to receive
messages.
Description
Checks for problems in the design or problems with design constraints. The check_timing command
performs a series of different checks based on user-specified variables and options. There is no default list
of checks. Use the -include option to specify which checks to perform. You must preceed check_timing
with update_timing_netlist.
The no_clock check reports whether registers have at least one clock at their clock pin, and that ports
determined to be clocks have a clock assigned to them, and also checks that PLLs have a clock assignment.
The multiple_clock check verifies that registers have at most one clock at their clock pin. (When multiple
clocks reach a register clock pin, it is undefined which clock is used for analysis.
The generated_clock check verifies that generated clocks are valid. Generated clocks must have a source
that is triggered by a valid clock.
The no_input_delay check verifies that every input port that is not determined to be a clock has an input
delay assignment.
The no_output_delay check verifies that every output port has an output delay constraint.
The partial_input_delay check verifies that input delays are complete, and ensures that input delays have
a rise-min, fall-min, rise-max, and fall-max portion set.
The partial_output_delay check verifies that output delays are complete, and makes sure that output
delays have a rise-min, fall-min, rise-max, and fall-max portion set.
The io_min_max_delay_consistency check verifies that min delay values specified by set_input_delay or
set_output_delay assignments are less than max delay values.
The reference_pin check verifies that reference pins specified in set_input_delay and set_output_delay
using the -reference_pin option are valid. A reference_pin is valid if the -clock option specified in the same
set_input_delay/set_output_delay command matches the clock that is in the direct fanin of the
reference_pin. Being in the direct fanin of the reference_pin means that there must be no keepers between
the clock and the reference_pin.
The latency_override check reports whether the clock latency set on a port or pin overrides the more
generic clock latency set on a clock. Clock latency can be set on a clock, where the latency applies to all
keepers clocked by the clock, whereas clock latency can also be set on a port or pin, where the latency
applies to registers in the fanout of the port or pin.